Memories are widely well known which have a memory back-up function to maintain information using a battery in case of a power failure. If the memory is a DRAM, it is essential, in the memory back-up control, for the DRAM to a refresh operation.
Usually, a refresh operation of a DRAM may be performed according to a row address strobe (RAS) only refresh (ROR) method or a column address strobe (CAS) before RAS (CBR) method or a self-refresh method. However, the CBR method is usually employed in performing a refresh operation for memory back-up control in case of power failure. The ROR method may be used in performing a refresh operation for memory back-up control in case of power failure. However, this method requires setting of fresh addresses each time upon performing refresh operation. Further, the refresh addresses must be handed over during a shift from memory back-up operation to a usual or normal operation or vice versa causing increased complexity of memory back-up control. This explains why the ROR method has not been widely employed.
Conventionally, few computer memory controllers are designed to provide a self-refresh function of a DRAM operable to perform a refresh operation when a memory back-up operation is needed. This is because DRAMs with a self-refresh function are not yet popular in the market and thus the number of such DRAMs is very small.
Accordingly, it is the conventional practice to use the CBR method in performing a refresh operation upon memory back-up operation using a battery as shown, for example, in JP-A 3-237678, which is illustrated in FIG. 4. In FIG. 4, the reference numeral 44 indicates a clock generator, which generates a refresh RAS signal (RRS signal) 48 and a refresh clock source signal (RFCK signal) 46. The reference numeral 45 indicates a refresh switch. A power failure signal (PF signal) 43 is used as an input to the refresh switch 45 for the refresh switch 45 to output a switch signal 47. The level of the PF signal 43 determines the level of the switch signal 47. RAS signal 41 and RFCK signal 46 are also used as inputs to the refresh switch 45, causing the refresh switch 45 to generate a refresh CAS signal (RCS signal) 49. The reference numerals 4A and 4B designate a RAS selector and a CAS selector, respectively. RAS signal 41 and RRS signal 48 are used as inputs to the RAS selector 4A. CAS signal 42 and RCS signal 49 are used as inputs to the CAS selector 4B. In response to the refresh switch signal 47, the RAS selector 4A selects one of its inputs for output to a DRAM 4C, and the CAS selector 4B selects one of its inputs for output to the DRAM 4C. This accomplishes a refresh operation mode necessary for assuring contents stored in the memory are maintained.
The timing chart of FIG. 5 illustrates operation of the conventional example shown in FIG. 4. During usual operation mode, RAS signal 41 and CAS signal 42 are fed to DRAM 4C. As illustrated in FIG. 5, the ROR method is used for refresh operation during normal operation mode, while the CBR method is used for refresh operation during back-up operation.
According to the conventional computer controller, the CBR method, which is employed for refresh operation during back-up mode operation, consumes a great amount of electricity out of a limited amount of electric power battery supply. Thus, the time period that the memory can be backed up is reduced. This is because the power consumption by DRAM during refresh operation according to a CBR method is as great as that during a usual operation.
To remedy this problem, it may be an alternative to employ a self-refresh operation of DRAM by redesigning a computer memory controller. However, the computer memory controller as redesigned poses a potential problem that it cannot provide a memory back-up function when a DRAM without a self-refresh function is installed. As mentioned before, the number of DRAMs with self-refresh function is limited in the market and most of the DRAMs available in the market are not provided with a self-refresh function, which requires a CBR method for refresh operation.
An object of the present invention is to provide a computer memory controller, which is operable to reduce power consumption during memory back-up operation within a DRAM having memory back-up function.
A further object of the present invention is to provide a computer memory controller, which is operable to select a refresh operation during a memory back-up mode in the case that DRAM is installed that is not provided with a special refresh function, such as a self-refresh function, needed for reducing power consumption.